1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to dynamic adjustment of timing in an integrated circuit configuration susceptible to data-dependent creep in device characteristics.
2. Description of the Related Art
Typically, modern semiconductor memories (whether embodied in a memory integrated circuit or incorporated in a larger designs, e.g., as cache memory of a processor integrate circuit) employ differential bit lines and some sort of differential amplifier or sensing circuit in their design. Such differential amplifier and sensing circuits are commonly known as sense amplifiers (sense amps) and a wide variety of sense amp designs are known in the art, including current sensing and voltage sensing variations.
Generally, when designing memory sense amps, great care is taken to optimize timing. Typically, a signal such as a strobe or equalization signal (EQ) is used to time sense amp operation. For example, transitions in an EQ signal are often used to equalize the sense amp nodes (SA and SA_1) for a period that allows opposing bit-lines (BL and BL_1) to develop sufficient voltage differential to support sensing. Once the BL and BL_1 have developed sufficient differential, EQ is transitioned to cause the sense amp to actually sense the developed differential.
If the period defined by an EQ transition is too short, then the bit-lines may not develop sufficient differential for the sense amp to correctly sense the data being read from an addressed memory cell. On the other hand, if too much time is allowed for EQ, then access time of the memory circuit is increased and achievable operating frequency (or at least memory access bandwidth) may be reduced. Therefore, in high-speed designs, the EQ signal delay path is designed to deliver the EQ transition at just the right time to ensure that correct data is being read, while aiming to minimize shortest cycle time.
The xe2x80x9cright timexe2x80x9d is typically a function of variations, potentially wafer-to-wafer variations or chip-to-chip variations, in the fixed electrical characteristics of fabricated circuits. To compensate for such variations, metal options may be added to a design to allow an EQ signal delay path to be tuned to the particular requirements of an integrated circuit. For example, a focused ion bean (FIB) fix may be employed to cut the EQ metal and insert additional buffering into the EQ signal path. Unfortunately, such a fix is both costly and only ensures that the EQ signal is appropriate at the time of the FIB fix.
In some conventional memory designs, variable delay paths have been introduced to accommodate a variety of supply voltage levels. See e.g., U.S. Pat. Nos. 5,638,333 and 5,764,178, in which a variety of circuits are described for introducing a variable delay in a signal path of sense amp timing signal. Typically, such circuits have been used to appropriately adapt sense amp timing in memory circuits operable at more than one supply voltage level. In other conventional memory designs, matched delay paths have been used to track variations in operating environment of semiconductor memory circuits. For example, sense amplifier delay circuits have been used to match response of a sense amplifier delay circuit with memory array temperature and voltage supply variations that affect array timing. See e.g., U.S. Pat. No. 6,072,733.
Unfortunately, in certain very-small device technologies, data-dependent effects have begun to present themselves and circuits developed to accommodate variations in supply voltage or to tune timing paths to temperature or supply voltage variables do not adequately address these data-dependent effects. One such effect is Negative Bias Temperature Instability (NBTI). Accordingly, new techniques are desired to address NBTI and other similar or related effects.
It has been discovered that post-manufacture variation of timing may be employed to address data-dependent degradation or creep in device characteristics affecting a differential circuit. One particular example of such data-dependent degradation or creep involves Negative Bias Temperature Instability (NBTI). In certain memory circuit configurations, NBTI can cause threshold voltage (Vt) of PMOS devices to increase by an amount that depends on the historical amount of voltage bias that has been applied across gate and source/drain nodes. In the case of many sense amplifier designs, a predominance of one value read out using the sense amp may tend to disparately affect one device (or set of devices) as compared with an opposing device (or set of devices). In other words, if the same data value is read over and over again, then one of two opposing PMOS devices of a typical sense amp will accumulate an NBTI-related Vt shift, while the opposing PMOS device will accumulate little or no shift. The accumulated mismatch tends to cause an increase in the sense amp fail-point.
For data-dependent degradation or creep such as that associated with NBTI effects on opposing PMOS devices, conventional techniques that employ manufacturing or circuit qualification stage fixes do not allow compensation for characteristic mismatch developed post-manufacture. Similarly, conventional matched delay circuits are generally insensitive to data-dependent degradation or creep. In contrast, techniques, circuits and methods described herein provide variable delay compensation for data-dependent mismatch in a characteristic of opposing devices, such as NBTI-related Vt shift based on disparate bias histories of opposing PMOS devices of a sense amplifier of a memory circuit.
In one embodiment in accordance with the present invention, a sensing circuit for a differential pair in a semiconductor memory includes transistors configured in opposition and a variable delay element responsive to an accumulated data-dependent mismatch in characteristics of the opposing transistors. The variable delay element at least partially compensates for the characteristic mismatch by varying latency of a sensing operation of the sensing circuit. In some variations, the compensated for data-dependent mismatch results, at least in part, from an effect that disparately affects one of the transistors as compared with the other, wherein the disparate effect is based on a skew in a history of values read out from associated memory elements. In some variations, the disparate effect is associated with negative bias temperature instability. In some variations, the transistors are PMOS devices, the characteristics are threshold voltage (Vt) and the disparate effect involves a monotonic increase in Vt based of disparate voltage bias histories of the PMOS devices.
In another embodiment in accordance with the present invention, a method of operating a semiconductor memory includes reading from and writing to addressable locations of the semiconductor memory under control of a program executing on a processor coupled thereto and performing an in-situ test operation and, responsive to failure indication consistent with an accumulated data-dependent disparity between operating characteristics of opposing devices of a sensing circuit, increasing latency of a sensing circuit control signal to accommodate the disparity. In some variations, the method further includes (i) performing, subsequent to the latency increase, additional read from and write to addressable locations of the semiconductor memory, (ii) performing a second in-situ test operation, and (iii) reducing latency of the sensing circuit control signal in accordance with a reduction an accumulated data-dependent disparity between operating characteristics of opposing devices of a sensing circuit.
In still another embodiment in accordance with the present invention, a method of compensating for accumulated data-dependent post-manufacture creep in a characteristic of one or more devices of a sensing circuit of a semiconductor memory includes: performing an in-situ test operation that writes data to and reads data from at least selected elements of the semiconductor memory, and varying latency in a control signal path leading to the sensing circuit to achieve identity between the written and read data. The latency variation at least partially compensates for the characteristic
In still another embodiment in accordance with the present invention, an integrated circuit includes a sensing circuit and a variable delay element. The sensing circuit is susceptible to an accumulated data-dependent post-manufacture creep in a characteristic of a device thereof, which affects optimal timing of the sensing circuit. The variable delay element is introducible in a timing path coupled to the sensing circuit and is responsive to an operating symptom of the characteristic creep. In some variations, the integrated circuit further includes a test circuit, wherein the variable delay element responsive to the test circuit. In some variations, the operating symptom includes a read after write failure.
In still yet another embodiment in accordance with the present invention, an integrated circuit chip compensates for disparate accumulated data-dependent post-manufacture creep in a characteristic of opposing devices of a sense amplifier at least in part by varying a latency of a sense amplifier control signal. In some variations, the opposing devices are PMOS devices and the characteristic is a threshold voltage (Vt) of the PMOS devices.
In still yet another embodiment in accordance with the present invention, an apparatus includes means for sensing a differential pair in a semiconductor memory and means for varying delay of a sensing operation of the sensing means. The variable delay means is responsive to an accumulated data-dependent mismatch in characteristics of opposing devices of the sensing means, wherein the variable delay means, when employed, at least partially compensates for the characteristic